Since the invention of the integrated circuit, the semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As the demand for miniaturization continues, the further shrinking of the process node may increase the complexity of fabricating integrated circuits.
As semiconductor technologies evolve, semiconductor fabrication processes have become more sophisticated and hence require complex equipment and fixtures. In the semiconductor process, integrated circuits are fabricated on a semiconductor wafer. The semiconductor wafer goes through many processing steps before a plurality of integrated circuits are separated by cutting the semiconductor wafer. The processing steps may include lithography, etching, doping and depositing different materials.
Etching is a processing step by which one or several layers can be removed from a wafer. There are two types of etching: wet etching and dry etching. Wet etching is an etching process that utilizes liquid chemicals to remove materials on top of a wafer. On the other hand, dry etching is an etching process that uses either plasma and/or reactive gases to remove materials from the wafer. Generally, a semiconductor wafer may go through many etching steps before the etching process is complete. Such etching steps include nitride etch, poly etch, spacer etch, contact etch, via etch, metal etch and the like.
Plasma is an ionized gas, which generates ions. The strength of ion bombardment is mainly determined by a dc bias of a plasma chamber. The dc bias is approximately proportional to the amplitude of a radio frequency (RF) power source used to power the plasma chamber. In a dry etching process, in order to control the etching rate, for example reducing the etching rate of a plasma chamber, the amplitude of the RF power source is reduced so that the dc bias of the plasma chamber is reduced too. As a result, the ion bombardment energy is reduced too. Such a reduction of the ion bombardment energy will reduce the etching rate of a wafer placed in the plasma chamber.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.